The present invention relates to a method and/or architecture for implementing bus bridges generally and, more particularly, to a method and/or architecture for implementing bus bridges that segment bus.
High-speed processors, memory and peripherals require features and performance beyond what can currently be provided by the Advanced High-performance Bus (AHB) of the Advanced Microcontroller Bus Architecture (AMBA) specification defined by ARM Limited. The high-speed AMBA peripherals have created needs for enhancements to the AHB and for multiple AHBs in a single ASIC. High performance 64-bit processors commonly need to be interfaced to 64-bit high speed memory and peripheral circuits and 32-bit memory and peripheral circuits. A conventional approach is to connect all memory circuits and peripheral circuits with a single AHB bus. Another conventional approach is to connect the 64-bit circuits and the 32-bit circuits to different AHB buses and communicate between busses through mailboxes or similar devices.
The conventional single-bus approach degrades a performance of the AHB bus and the processor. Connecting the 64-bit memory circuits and 32-bit peripherals on a single 64-bit bus requires the processor to do 32-bit accesses to the peripherals. The processor needs to differentiate between the 64-bit and 32-bit devices to ensure that a 64-bit access is not performed to a 32-bit device. Existing software must be modified to ensure that the processor does not generate an incorrect type of bus transaction. The 64-bit AHB bus will not be fully utilized since the 32-bit peripherals will only use xc2xd of an available throughput. Furthermore, the 32-bit transactions lower an overall bandwidth that is available to other 64-bit masters on the AHB bus.
The conventional dual-bus approach creates complexity. Connecting the 64-bit circuits to a 64-bit AHB bus and the 32-bit circuits to a 32-bit AHB bus requires the processor to interface with and communicate on both busses simultaneously. The software must be modified to distinguish which memory circuits and peripherals are on which bus. Additionally, multiple processors on the 64-bit AHB bus must coordinate with each other when transferring data between the busses.
The present invention concerns a bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width. The second interface may be connectable to a second bus having a second data width narrower than the first data width. The plurality of registers may be configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between the first bus and the second bus. The controller configured to control the registers.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing bus bridges that may (i) segment a bus for legacy peripheral compatibility, (ii) operate at a high clock frequency, (iii) run each bus segment at a different rate, (iv) provide for a similar native bus width on each segment, (v) provide for different native bus widths on each segment, (vi) perform endianess conversions between the segments, (vii) make the native bus width of the legacy peripherals transparent to the software, (viii) increase an overall bus bandwidth available to other 64-bit bus masters on the same bus segment, and/or (ix) reduce capacitive loading on the bus segments.